Eaton EDR 3000 - Page 213

EDR-3000 IM02602003E
Name Description
Logic.LE20.Out Signal: Latched Output (Q)
Logic.LE20.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE21.Gate Out Signal: Output of the logic gate
Logic.LE21.Timer Out Signal: Timer Output
Logic.LE21.Out Signal: Latched Output (Q)
Logic.LE21.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE22.Gate Out Signal: Output of the logic gate
Logic.LE22.Timer Out Signal: Timer Output
Logic.LE22.Out Signal: Latched Output (Q)
Logic.LE22.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE23.Gate Out Signal: Output of the logic gate
Logic.LE23.Timer Out Signal: Timer Output
Logic.LE23.Out Signal: Latched Output (Q)
Logic.LE23.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE24.Gate Out Signal: Output of the logic gate
Logic.LE24.Timer Out Signal: Timer Output
Logic.LE24.Out Signal: Latched Output (Q)
Logic.LE24.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE25.Gate Out Signal: Output of the logic gate
Logic.LE25.Timer Out Signal: Timer Output
Logic.LE25.Out Signal: Latched Output (Q)
Logic.LE25.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE26.Gate Out Signal: Output of the logic gate
Logic.LE26.Timer Out Signal: Timer Output
Logic.LE26.Out Signal: Latched Output (Q)
Logic.LE26.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE27.Gate Out Signal: Output of the logic gate
Logic.LE27.Timer Out Signal: Timer Output
Logic.LE27.Out Signal: Latched Output (Q)
Logic.LE27.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE28.Gate Out Signal: Output of the logic gate
Logic.LE28.Timer Out Signal: Timer Output
Logic.LE28.Out Signal: Latched Output (Q)
Logic.LE28.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE29.Gate Out Signal: Output of the logic gate
Logic.LE29.Timer Out Signal: Timer Output
Logic.LE29.Out Signal: Latched Output (Q)
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