Eaton EDR 3000 - Page 344

EDR-3000 IM02602003E
Name Description
Logic.LE25.Gate Out Signal: Output of the logic gate
Logic.LE25.Timer Out Signal: Timer Output
Logic.LE25.Out Signal: Latched Output (Q)
Logic.LE25.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE26.Gate Out Signal: Output of the logic gate
Logic.LE26.Timer Out Signal: Timer Output
Logic.LE26.Out Signal: Latched Output (Q)
Logic.LE26.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE27.Gate Out Signal: Output of the logic gate
Logic.LE27.Timer Out Signal: Timer Output
Logic.LE27.Out Signal: Latched Output (Q)
Logic.LE27.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE28.Gate Out Signal: Output of the logic gate
Logic.LE28.Timer Out Signal: Timer Output
Logic.LE28.Out Signal: Latched Output (Q)
Logic.LE28.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE29.Gate Out Signal: Output of the logic gate
Logic.LE29.Timer Out Signal: Timer Output
Logic.LE29.Out Signal: Latched Output (Q)
Logic.LE29.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE30.Gate Out Signal: Output of the logic gate
Logic.LE30.Timer Out Signal: Timer Output
Logic.LE30.Out Signal: Latched Output (Q)
Logic.LE30.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE31.Gate Out Signal: Output of the logic gate
Logic.LE31.Timer Out Signal: Timer Output
Logic.LE31.Out Signal: Latched Output (Q)
Logic.LE31.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE32.Gate Out Signal: Output of the logic gate
Logic.LE32.Timer Out Signal: Timer Output
Logic.LE32.Out Signal: Latched Output (Q)
Logic.LE32.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE33.Gate Out Signal: Output of the logic gate
Logic.LE33.Timer Out Signal: Timer Output
Logic.LE33.Out Signal: Latched Output (Q)
Logic.LE33.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE34.Gate Out Signal: Output of the logic gate
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