EasyManua.ls Logo

Eaton EDR 3000 - Page 613

Eaton EDR 3000
770 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
EDR-3000 IM02602003E
Name Description
IEC61850.VirtInp8 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp9 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp10 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp11 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp12 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp13 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp14 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp15 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp16 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp17 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp18 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp19 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp20 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp21 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp22 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp23 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp24 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp25 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp26 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp27 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp28 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp29 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp30 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp31 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp32 Signal: Virtual Input (IEC61850 GGIO Ind)
Logic.LE1.Gate Out Signal: Output of the logic gate
Logic.LE1.Timer Out Signal: Timer Output
Logic.LE1.Out Signal: Latched Output (Q)
Logic.LE1.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate Out Signal: Output of the logic gate
Logic.LE2.Timer Out Signal: Timer Output
Logic.LE2.Out Signal: Latched Output (Q)
Logic.LE2.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate Out Signal: Output of the logic gate
Logic.LE3.Timer Out Signal: Timer Output
Logic.LE3.Out Signal: Latched Output (Q)
Logic.LE3.Out inverted Signal: Negated Latched Output (Q NOT)
www.eaton.com 601

Table of Contents

Related product manuals