Eaton EDR 3000 - Page 750

EDR-3000 IM02602003E
Name Description
Logic.LE53.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE53.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE54.Gate Out Signal: Output of the logic gate
Logic.LE54.Timer Out Signal: Timer Output
Logic.LE54.Out Signal: Latched Output (Q)
Logic.LE54.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE54.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE54.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE54.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE54.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE54.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE55.Gate Out Signal: Output of the logic gate
Logic.LE55.Timer Out Signal: Timer Output
Logic.LE55.Out Signal: Latched Output (Q)
Logic.LE55.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE55.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE55.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE55.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE55.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE55.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE56.Gate Out Signal: Output of the logic gate
Logic.LE56.Timer Out Signal: Timer Output
Logic.LE56.Out Signal: Latched Output (Q)
Logic.LE56.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE56.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE56.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE56.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE56.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE56.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE57.Gate Out Signal: Output of the logic gate
Logic.LE57.Timer Out Signal: Timer Output
Logic.LE57.Out Signal: Latched Output (Q)
Logic.LE57.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE57.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE57.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE57.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE57.Gate In4-I State of the module input: Assignment of the Input Signal
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