Edge-Core AS7326-56X - Page 148

EDGECORE NETWORKS CORPORATION 2018
148
0x4F
QSFP28 RGB LED -32
Read &Write
0x07
0x50
SFP+ RGB LED -1
Read &Write
0x07
0x51
SFP+ RGB LED -2
Read &Write
0x07
0x60
MGMT LED
Read &Write
0x03
5.12.6.1. Offset 0x01 CPLD version (Read Only)
Bit
Name
R/W
Reset Value
Description
7:0
CPLD_ver[7:0]
R
0x02
CPLD version
5.12.6.2. Offset 0x02 CPLD interrupt (Read & Write)
Bit
Name
R/W
Reset Value
Description
7:1
Reserved
NA
NA
0
CPLD3_INT
R/W
1
1:No interrupt(Default)
0: Sent interrupt request to CPLD1
5.12.6.3. Offset 0x10 SFP28 RGB LED -1 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7:6
Reserve
NA
NA
5
Port34_Active_B
(P34_Lane1_LED_B)
R/W
0
1: Port34_B Active ON
0: Port34_B Active OFF (Default)
4
Port34_Active_G
(P34_Lane1_LED_G)
R/W
0
1: Port34_G Active ON
0: Port34_G Active OFF (Default)
3
Port34_Active_R
(P34_Lane1_LED_R)
R/W
0
1: Port34_R Active ON
0: Port34_R Active OFF (Default)
2
Port34_B
(P34_Lane1_LED_B)
R/W
1
1: Port34_B LED OFF (Default)
0: Port34_B LED ON
1
Port34_G
(P34_Lane1_LED_G)
R/W
1
1: Port34_G LED OFF (Default)
0: Port34_G LED ON
0
Port34_R
(P34_Lane1_LED_R)
R/W
1
1: Port34_R LED OFF (Default)
0: Port34_R LED ON
5.12.6.4. Offset 0x11 SFP28 RGB LED -2 (Read& Write)
Bit
Name
R/W
Reset Value
Description
7:6
Reserve
NA
NA
5
Port35_Active_B
(P33_Lane0_LED_B)
R/W
0
1: Port35_B Active ON
0: Port35_B Active OFF (Default)
4
Port35_Active_G
(P33_Lane0_LED_G)
R/W
0
1: Port35_G Active ON
0: Port35_G Active OFF (Default)