Edge-Core AS7326-56X - Page 28

EDGECORE NETWORKS CORPORATION 2018
28
GPIO53
1
1
1k pull to gnd
GPIO54
X
X
NC
GPIO55
1
1
FM_BIOS_RCRV_BOOT_N
GPIO57
1
1
FM_ME_RCRV_N
GPIO58
0
X
SML1_CLK
GPIO59
1
X
XDP_NOA0_PCH/
USB1_PWRFAULT
GPIO60
0
X
SML0ALERT#
GPIO61
X
X
NC
GPIO62
1
0
PCH_SUSCLK_33K
GPIO65
X
X
NC
GPIO67
X
X
NC
GPIO68
X
X
NC
GPIO69
X
X
NC
GPIO70
X
X
NC
GPIO71
X
X
NC
GPIO72
1
1
1K pull to 3.3V
GPIO74
0
X
SML1ALERT#/TEMP_ALERT#.
GPIO75
0
X
SML1DATA
Table 4 PCH Strap definitions
Strap pin
description
value
SATA1GP/ GPIO19
This field determines the destination of accesses
to the BIOS memory range. Also controllable
using Boot BIOS Destination bit (Chipset Config
Registers: Offset 3410h:Bit 10). This strap is used
in conjunction with Boot BIOS Destination
Selection 1 strap.
Bit11 Bit 10 Boot BIOS Destination
0 1 Reserved
1 0 Reserved
1 1 SPI (default)
0 0 LPC
1
GPIO51
This field determines the destination of accesses
to the BIOS memory range. Also controllable
using Boot BIOS Destination bit (Chipset Config
Registers: Offset 3410h:Bit 11). This strap is used
1