Edge-Core AS7326-56X - Page 34

EDGECORE NETWORKS CORPORATION 2018
34
IDE bus master
Anywhere in 64KB I/O space
1. 16 or 32
2. 16
1. SATA host controller #1, #2
2. IDE-R
Native IDE command
Anywhere in 64KB I/O space
8
1. SATA host controller #1, #2
2. IDE-R
Native IDE control
Anywhere in 64KB I/O space
4
1. SATA host controller #1, #2
2. IDE-R
SATA index/data pair
Anywhere in 64KB I/O space
16
1. SATA host controller #1, #2
2. IDE-R
SMBus
Anywhere in 64KB I/O space
32
SMB unit
TCO
96 bytes above ACPI base
32
TCO unit
GPIO
Anywhere in 64KB I/O space
128
GPIO unit
Parallel port
3 ranges in 64KB I/O space
8
LPC peripheral
Serial port 1
8 ranges in 64KB I/O space
8
LPC peripheral
Serial port 2
8 ranges in 64KB I/O space
8
LPC peripheral
Floppy disk controller
2 ranges in 64KB I/O space
8
LPC peripheral
LAN
Anywhere in 64KB I/O space
32
LAN unit
LPC generic 1
Anywhere in 64KB I/O space
4 to 256
LPC peripheral
LPC generic 2
Anywhere in 64KB I/O space
4 to 256
LPC peripheral
LPC generic 3
Anywhere in 64KB I/O space
4 to 256
LPC peripheral
LPC generic 4
Anywhere in 64KB I/O space
4 to 256
LPC peripheral
I/O trapping ranges
Anywhere in 64KB I/O space
1 to 256
Trap on backbone
PCI bridge
Anywhere in 64KB I/O space
I/O base/limit
PCI bridge
PCI-E root ports
Anywhere in 64KB I/O space
I/O base/limit
PCI-E root ports 1-8
KT
Anywhere in 64KB I/O space
8
KT
Table 8 Memory decode ranges from processor perspective
Memory range
target
Dependency/comments
0000 0000h-000D FFFFh
0010 0000h-TOM
Main memory
TOM registers in host controller
000E 0000h-000E FFFFh
LPC or SPI
Bit 6 in BIOS decode enable register is set
000F 0000h-000F FFFFh
LPC or SPI
Bit 7 in BIOS decode enable register is set
FEC_ _000h-FEC_ _040h
IOx APCI inside broadwell-de SoC
_ _ is controlled using APIC range select (ASEL)
field and APIC enable (AEN) bit.
FEC1 0000h-FEC1 7FFFh
PCI-E port 1
PCI-E root port 1 I/OxAPIC enable (PAE) set
FEC1 8000h-FEC1 FFFFh
PCI-E port 2
PCI-E root port 2 I/OxAPIC enable (PAE) set
FEC2 0000h-FEC2 7FFFh
PCI-E port 3
PCI-E root port 3 I/OxAPIC enable (PAE) set
FEC2 8000h-FEC2 FFFFh
PCI-E port 4
PCI-E root port 4 I/OxAPIC enable (PAE) set
FEC3 0000h-FEC3 7FFFh
PCI-E port 5
PCI-E root port 5 I/OxAPIC enable (PAE) set
FEC3 8000h-FEC3 FFFFh
PCI-E port 6
PCI-E root port 6 I/OxAPIC enable (PAE) set
FEC4 0000h-FEC4 7FFFh
PCI-E port 7
PCI-E root port 7 I/OxAPIC enable (PAE) set
FEC4 8000h-FEC4 FFFFh
PCI-E port 8
PCI-E root port 8 I/OxAPIC enable (PAE) set
FFC0 0000h-FFC7 FFFFh
FF80 0000h- FF87 FFFFh
LPC or SPI (or PCI)
Bit 8 in BIOS decode enable register is set
FFC8 0000h-FFCF FFFFh
LPC or SPI (or PCI)
Bit 9 in BIOS decode enable register is set