Edge-Core AS7326-56X - Page 56

EDGECORE NETWORKS CORPORATION 2018
56
GPIO2
0
X
NC
GPIO3
0
X
NC
GPIO4
1
1
CPU to PCH Throttle event
interrupt
GPIO5
0
X
NC
GPIO6
1
0
JTAG enable, enable JTAG
multiplexer to update CPLD code
from CPU.
1: enable the JTAG multiplexer
0: disable the JTAG multiplexer
GPIO7
0
X
NC
GPIO8
1
0
JTAG Multiplexer select, which
select the JTAG signals from CPU
would go to CPLD or main board
1: to CPLD (default)
0: to Main board
GPIO9
1
0
XDP_NOA5_PCH/
BDX_CPLD_JTAG_TDI
When configure to be
BDX_CPLD_JTAG_TDI, which is CPU
JTAG output
GPIO10
1
1
XDP_NOA6_PCH/
BDX_CPLD_JTAG_TDO
When this pin configure to
BDX_CPLD_JTAG_TDO
, which is CPU JTAG input
GPIO11
0
X
SMBALERT#
GPIO12
1
0
Reset MAC, to do the sleep
function.
GPIO14
1
0
XDP_NOA7_PCH/
BDX_CPLD_JTAG_TCK
GPIO15
1
0
SOC_FPGA_CLK
GPIO16
1
0
FM_THROTTLE_PCH_N/
FM_THROTTLE_N
GPIO17
1
1
BMC present detect