Chapter 12. Performance 447
Clock frequency at 4.3 GHz
IBM CMOS 14S0 22 nm SOI technology with IBM eDRAM technology
The z13s design has the following enhancements as compared with the zBC12:
Increased total number of PUs that are available on the system, from 18 to 26, and
number of characterizable cores, from 13 to 20. There is a maximum of 6 CPs.
Hardware system area (HSA) increased from 16 GB to 40 GB
Increased number of supported LPARs from 30 to 40
2 TB of addressable memory (configurable to LPARs) with up to 2 TB of memory per LPAR
Increased default number of SAP processors up to 3 on a Model N20
New Coupling Facility Control Code (CFCC) that is available for improved performance:
– Elapsed time improvements when dynamically altering the size of a cache structure
– DB2 conditional writes to a group buffer pool (GBP)
– Performance improvements for coupling facility cache structures to avoid flooding the
coupling facility cache with changed data, and avoid excessive delays and backlogs for
cast-out processing
– Performance throughput enhancements for parallel cache castout processing by
extending the number of record code check (RCC) cursors beyond 512
– Coupling facility (CF) storage class and castout class contention avoidance by
breaking up individual storage class and castout class queues to reduce storage class
and castout class latch contention
The following new features are available on the z13s:
Integrated Coupling Adapter (ICA SR)
FICON Express16S
Shared Memory Communications over RDMA (SMC-R). The 10GbE Remote Direct
Memory Access (RDMA) over Converged Ethernet (RoCE) Express (10GbE RoCE
Express) feature now supports using both physical ports and can be shared between up to
31 LPARs.
Shared Memory Communications-Direct Memory Access (SMC-D) over Internal Shared
Memory (ISM)
Crypto Express5S with up to 40 domains
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