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Intel Stratix 10 Configuration User Guide
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Figure 47.
Fitter Report and SDM_IO Pin Reporting
Starting with the Intel Quartus Prime Pro Edition Software, version 18.1, an SDM
debug tool is available through the S
ystem Console,
Tools
➤
System Debugging
Tools
➤
System Console
➤
Stratix 10 SDM Debug
.
6. Intel Stratix 10 Debugging Guide
UG-S10CONFIG | 2018.11.02
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Intel Stratix 10 Configuration User Guide
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Table of Contents
Default Chapter
2
Table of Contents
2
1 Intel ® Stratix ® 10 Configuration Overview
4
Configuration and Related Signals
7
Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices
8
Intel Stratix 10 Configuration Architecture
8
Secure Device Manager
9
2 Intel Stratix 10 Configuration Details
12
Configuration Flow Diagram
12
Intel Stratix 10 Configuration Timing Diagram
14
Additional Clock Requirements for Transceivers, HPS, Pcie, High Bandwidth Memory (HBM2) and Smartvid
16
Intel Stratix 10 Configuration Pins
17
SDM Pin Mapping
17
MSEL Settings
18
Device Configuration Pins
19
Setting Additional Configuration Pins
21
Enabling Dual-Purpose Pins
22
Setting Configuration Clock Source
23
Configuration Clocks
24
OSC_CLK_1 Clock Input
24
Configuration and Programming Files
25
3 Intel Stratix 10 Configuration Schemes
27
Avalon-ST Configuration
27
Enabling Avalon-ST Device Configuration
28
Avalon-ST Configuration Timing
28
Avalon-ST Single-Device Configuration
30
RBF Configuration File Format
32
Debugging Guidelines for the Avalon-ST Configuration Scheme
33
IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
34
AS Configuration
51
AS Single-Device Configuration
51
AS Using Multiple Serial Flash Devices
52
AS Configuration Timing
53
Programming Serial Flash Devices
54
Serial Flash Memory Layout
56
As_Clk
57
Active Serial Configuration Software Settings
58
Generating and Programming as Configuration Programming Files
59
Debugging Guidelines for the as Configuration Scheme
61
Configuration from SD MMC
62
SD MMC Single-Device Configuration
62
JTAG Configuration
63
JTAG Single-Device Configuration
64
JTAG Multi-Device Configuration
66
Debugging Guidelines for the JTAG Configuration Scheme
67
4 Stratix 10 Configuration Features
69
Device Security
69
Configuration Via Protocol
69
Partial Reconfiguration
71
5 Remote System Upgrade
72
Remote System Upgrade Functional Description
74
Remote System Upgrade Using as Configuration
74
Remote System Upgrade Configuration Images
75
Remote System Upgrade Configuration Sequence
76
Guidelines for Performing Remote System Upgrade Functions for Non-HPS
77
Commands and Error Codes
78
Operation Commands
79
Error Code Responses
82
Remote System Upgrade Flash Device Layout
83
Configuration Firmware Pointer Block (CPB)
83
Generating Remote System Upgrade Image Files Using Programming File Generator
84
Generating a Standard RSU Image
84
Generating a Single RSU Image
85
Remote System Upgrade from FPGA Core Example
86
Prerequisites
87
Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
87
Programming Flash Memory with Initial Remote System Upgrade Image
91
Reconfiguring the Device with an Application or Factory Image
92
Adding an Application Image
93
Removing Application Image
96
6 Intel Stratix 10 Debugging Guide
98
Intel Stratix 10 Debugging Overview
98
Configuration Pin Differences from Previous Device Families
98
Configuration File Format Differences
100
Understanding and Troubleshooting Configuration Pin Behavior
100
Nconfig
101
Nstatus
102
CONF_DONE and INIT_DONE
102
SDM_IO Pins
103
7 Intel Stratix 10 Configuration User Guide Archives
106
8 Document Revision History for the Intel Stratix 10 Configuration User Guide
107
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Intel Stratix 10 Specifications
General
Brand
Intel
Model
Stratix 10
Category
Control Unit
Language
English
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