Intel Stratix 10 Configuration User Guide

3.1.3. Avalon-ST Single-Device Configuration
Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for additional
information about individual pin usage and requirements.
Figure 8. Connections for Avalon-ST x8 Single-Device Configuration
Intel® Stratix®10
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
AVST_DATAx8 [7:0]
AVSTx8_VALID
AVST_READY
AVST_CLK
Configuration
Data Signals
Configuration
Control Signals
Compact Flash Interface
External Compact Flash Memory
ADDR DATA
.rbf
(little endian)
Control
CPLD / FPGA
External Host
fpga_clk
fpga_ready
fpga_valid
fpga_conf_done
fpga_nstatus
fpga_nconfig
fpga_data [7:0]
Parallel Flash Loader II IP
or
Microprocessor
or
Custom Logic
10kΩ
MSEL
V
CCIO_SDM
8
3
Synchronizers
External Clock Source
(2)
(1)
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
Send Feedback
30

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English