Intel Stratix 10 Configuration User Guide

Pin Type Weak Pull-
Up
Function
fpga_nconfig
Open Drain
Output
10-kW Pull-
Up Resistor
Connects to the nCONFIG pin of the FPGA. A low
pulse resets the FPGA and initiates configuration.
These pins are not available for the flash
programming option in the PFL II IP core.
(12)
pfl_reset_watchdog
Input — A switch signal to reset the watchdog timer before
the watchdog timer times out. Hold the signal high
or low for at least two clock cycles of the pfl_clk
frequency to correctly reset the watchdog timer.
pfl_watchdog_error
Output — A high signal indicates an error to the watchdog
timer.
Related Information
Avalon Interface Specifications
3.2. AS Configuration
In AS configuration schemes, the SDM block in the Intel Stratix 10 device controls the
configuration process and interfaces. The serial flash configuration devices store the
configuration data. During AS Configuration, the SDM first powers on with boot ROM.
Then, the SDM loads the initial configuration firmware from AS x4 flash. After the
configuration firmware loads, this firmware controls the remainder of the configuration
process, including I/O configuration and FPGA core configuration. Designs including an
HPS, can use the HPS to access serial flash memory after the initial configuration.
Note: The serial flash configuration device must be fully powered up at the same time or
before ramping up V
CCIO_SDM
of the Intel Stratix 10 device.
The AS configuration scheme supports AS x4 (4-bit data width) mode only.
Table 23. Intel Stratix 10 Configuration Data Width, Clock Rates, and Data Rates
Mode Data Width
(bits)
Max Clock Rate Max Data Rate MSEL[2:0]
Active Active Serial (AS)
4 133 MHz 532 Mbps Fast mode - 001
Normal mode -
011
Refer to the related information for more information about enabling other flash device
support.
Related Information
• Can I use 3rd party QSPI flash devices for Active Serial configuration of Intel
Stratix 10 devices?
• AS Configuration Timing in Intel Stratix 10 Devices
3.2.1. AS Single-Device Configuration
Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for additional
information about individual pin usage and requirements.
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
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Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English