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Intel Stratix 10 Configuration User Guide

Intel Stratix 10
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1. Intel
®
Stratix
®
10 Configuration Overview
1.1. Intel
®
Stratix
®
10 Configuration Overview
All Intel
®
Stratix
®
10 devices include a secure device manager (SDM) to manage
FPGA configuration and security. The SDM provides a failsafe, strongly authenticated,
programmable security mode for device configuration. Previous FPGA families include
a fixed state machine to manage device configuration.
The Intel Quartus
®
Prime software also provides flexible and robust security features
to protect sensitive data, intellectual property, and the device itself under both remote
and physical attacks. Configuration bitstream authentication ensures that the firmware
and configuration bitstream are from a trusted source. Encryption prevents theft of
intellectual property. The Intel Quartus Prime software also compresses FPGA
bitstreams, reducing memory utilization.
Intel describes configuration schemes from the point-of-view of the FPGA. Intel Stratix
10 devices support active and passive configuration schemes. In active configuration
schemes the FPGA acts as the master and the external memory acts as a slave device.
In passive configuration schemes an external host acts as the masters and controls
configuration. The FPGA acts as the slave device. All Intel Stratix 10 configuration
schemes support design security, remote system upgrade, and partial reconfiguration.
To implement remote system update in passive configuration schemes, an external
controller must store and drive the configuration bitstream.
Intel Stratix 10 devices support the following configuration schemes:
Avalon
®
Streaming (Avalon-ST)
JTAG
Configuration via Protocol (CvP)
Active Serial (AS) normal and fast modes
Secure Digital and Multi Media Card (SD MMC)
Table 1. Intel Stratix 10 Configuration Data Width, Clock Rates, and Data Rates
Mbps is an abbreviation for Megabits per second.
Configuration Scheme
Data Width (bits) MSEL[2:0]
Passive
Avalon-ST
32 000
16 001
8 110
JTAG 1 111
Configuration via Protocol (CvP) x1, x2, x4, x8, x16 lanes 001
continued...
UG-S10CONFIG | 2018.11.02
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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Intel Stratix 10 Specifications

General IconGeneral
BrandIntel
ModelStratix 10
CategoryControl Unit
LanguageEnglish

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