Intel Stratix 10 Configuration User Guide

SDM Pins MSEL
Function
Configuration Source Function Select Other
Functions
Avalon-ST x8 AS SD/MMC
SDM_IO13
—
AVSTx8_DATA5
—
SDMMC_CFG_DATA5 DIRECT_TO_FAC
TORY
SEU_ERROR
SDM_IO14
—
AVSTx8_CLK
— —
PWRMGT_SDA
DIRECT_TO_FAC
TORY
SDM_IO15
—
AVSTx8_DATA6
—
SDMMC_CFG_DATA6
DIRECT_TO_FACT
ORY
SEU_ERROR
SDM_IO16
— — — —
CONF_DONE
INIT_DONE
PWRMGT_SDA
DIRECT_TO_FAC
TORY
SEU_ERROR
Related Information
Intel Stratix 10 Device Pinouts
2.4.2. MSEL Settings
The MSEL[2:0] pins set the configuration scheme for Intel Stratix 10 devices. Use
4.7-kΩ resistors to pull the MSEL[2:0] pins up to V
CCIO_SDM
or down to ground as
required by the MSEL[2:0] setting for configuration scheme. You must also specify
the configuration scheme on the Configuration page of the Device and Pin Options
dialog box in the Intel Quartus Prime Software.
Figure 5. MSEL Pull-Up and Pull-Down Circuit Diagram
RUP
VCCIO_SDM
MSEL[0]
4.7kΩ
RDN
MSEL[0]
4.7kΩ
OR
Table 4. MSEL Settings for Each Configuration Scheme of Intel Stratix 10 Devices
Configuration Scheme MSEL[2:0]
Avalon-ST (x32) 000
Avalon-ST (x16) 101
Avalon-ST (x8) 110
AS (Fast mode – for CvP)
(2)
001
continued...
2. Intel Stratix 10 Configuration Details
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English