Intel Stratix 10 Configuration User Guide

Power Supply Status
The power-on reset (POR) holds the Intel Stratix 10 device in the reset state until the
power supply outputs are within the recommended operating range. t
RAMP
defines the
maximum power supply ramp time. If POR does not meet the t
RAMP
time, the Intel
Stratix 10 device I/O pins and programming registers remain tri-stated.
For more information about POR refer to the Intel Stratix 10 Power Management User
Guide. For more information about t
RAMP
refer to the Intel Stratix 10 datasheet.
Related Information
• Intel Stratix 10 Power Management User Guide
• Intel Stratix 10 Device Datasheet (Core and HPS)
• Should clocks and resets in user logic be gated until the configuration process is
completed in Intel Stratix 10?
2.3. Additional Clock Requirements for Transceivers, HPS, PCIe,
High Bandwidth Memory (HBM2) and SmartVID.
The Intel Stratix 10 device has additional clock requirements for transceivers, the
HPS, PCIe, SmartVID, and the High Bandwidth Memory (HBM2) IP.
Follow these guidelines to ensure successful device configuration and reconfiguration:
• For designs including the High Bandwidth Memory (HBM2) IP or any IP using
transceivers, you must provide a free running and stable reference clock to the
device before device configuration begins. All transceiver power supplies must be
at the required voltage.
Note: The transceivers must have their own power supplies. You can use the V
CC
and V
CCP
power supplies for initial transceiver testing. However, eventually
device configuration fails because transceiver calibration cannot complete.
• For the HPS, the HPS clock and HPS DDR clock must be present and stable before
configuration begins.
• For SmartVID devices, refer to the Intel Stratix 10 Power Management and VID
Interface Implementation Guide chapter in the Intel Stratix 10 Power Management
User Guide. This chapter provides instructions on assigning the VID Operation
mode, the PMBus mode pins, PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT,
and the required software settings.
• Designs that use any transceivers on the Intel Stratix 10 device must provide an
external, free-running, stable reference clock input to the OSC_CLK_1 pin before
device configuration begins.
2. Intel Stratix 10 Configuration Details
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English