Intel Stratix 10 Configuration User Guide

3. Intel Stratix 10 Configuration Schemes
3.1. Avalon-ST Configuration
The Avalon-ST configuration scheme is new in Intel Stratix 10 devices. It replaces the
FPP mode available in earlier device families. The Avalon-ST configuration scheme is
passive. Avalon-ST is the fastest configuration scheme for Intel Stratix 10 devices.
This scheme uses an external host, such as a microprocessor, MAX
®
II, MAX V, or
Intel MAX 10 device to drive configuration. The external host controls the transfer of
configuration data from an external storage such as flash memory to the FPGA. The
design that controls the configuration process resides in the external host. You can use
the PFL II IP core with a MAX II, MAX V, or Intel MAX 10 device as the host to read
configuration data from the flash memory device and configure the Intel Stratix 10
device.
Table 9. Avalon-ST Configuration Data Width, Clock Rates, and Data Rates
Protocol Data Width (bits) Max Clock Rate Max Data Rate MSEL[2:0]
Avalon-ST
32 125 MHz 4000 Mbps 000
16 125 MHz 2000 Mbps 001
8 125 MHz 1000 Mbps 110
Refer to the Intel Stratix 10 Datasheet for configuration timing estimates.
The Avalon-ST configuration scheme supports the following configuration methods:
• CPLD with PFL II and common flash interface (CFI) flash memory
• External host, typically a microprocessor, with any external memory
Note: You can use the Intel PFL II IP core as the configuration host. If you use a third-party
microprocessor, refer to the Avalon Streaming Interfaces in the Avalon Interface
Specifications for protocol details.
Related Information
• Avalon Interface Specifications
• Intel Stratix 10 Device Features
For a list of Intel Stratix 10 device features that are planned for future
releases.
UG-S10CONFIG | 2018.11.02
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English