Intel Stratix 10 Configuration User Guide

6.3. Configuration File Format Differences
Detailed information about the configuration file format is proprietary. This topic
explains the general structure and differences from previous device families.
The configuration file format differs significantly from previous device families. The
configuration bitstream begins with a SDM firmware section. The SDM loads the boot
ROM firmware during power-on reset. Design sections for I/O configuration, HPS boot
code (if applicable), and fabric configuration follow the firmware section. Configuration
begins after the SDM boot ROM performs device consistency checks.
Figure 45. Example of an Intel Stratix 10 Configuration Bitstream Structure
Firmware Section
Firmware section
is static and
Quartus Prime
version dependent
Design Section
(IO Configuration)
Design Section
(FPGA Core Configuration)
Design Section
(HPS boot code)
The firmware section is not part of the .sof file. The Intel Quartus Prime Pro Edition
Programmer adds the firmware to the to the .sof. The programmer adds the
firmware when configuring an Intel Stratix 10 device or when it converts the .sof to
another format.
6.4. Understanding and Troubleshooting Configuration Pin Behavior
Configuration typically fails for one of the following reasons:
• The host times outs
• A configuration data error occurs
• An external event interrupts configuration
• An internal error occurs
6. Intel Stratix 10 Debugging Guide
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English