Intel Stratix 10 Configuration User Guide

3.1.1. Enabling Avalon-ST Device Configuration
You enable the Avalon-ST device configuration scheme in the Intel Quartus Prime
software.
Complete the following steps to specify an Avalon-ST interface for device
configuration.
1. On the Assignments menu, click Device.
2. In the Device and Pin Options dialog box, select the Configuration category.
3. In the Configuration window, in the Configuration scheme dropdown list,
select the appropriate Avalon-ST bus width.
4. Click OK to confirm and close the Device and Pin Options dialog box.
3.1.2. Avalon-ST Configuration Timing
Before beginning configuration, trigger device cleaning by toggling the nCONFIG pin
from high to low to high. These nCONFIG transitions also return the device to the
configuration state.
Figure 7. Avalon-ST Bus Timing Waveform
AVST_CLK
AVST_READY
AVSTx8_VALID
or AVST_VALID
AVSTx8_DATA[7:0
AVST_DATA[15:0]
AVST_data[31:0]]
must deassert
within 6 cycles
data0 data1 data2 data3
The configuration files for Intel Stratix 10 devices can be highly compressed. During
configuration, the decompression of the bit stream inside the device requires the host
to pause before sending more data. The Intel Stratix 10 device asserts the
AVST_READY signal when the device is ready to accept data. The AVST_READY signal
is only valid when the nSTATUS pin is high. In addition, the host must handle
backpressure by monitoring the AVST_READY signal and may assert AVST_VALID
signal any time after the assertion of AVST_READY signal. The host must monitor the
AVST_READY signal throughout the configuration.
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English