Intel Stratix 10 Configuration User Guide

The AVST_READY signal sent by the Intel Stratix 10 device to the host is not
synchronized with the AVSTx8_CLK or AVST_CLK. To configure the Intel Stratix 10
device successfully, the host must adhere to the following constraints:
• The host must drive no more than six data words after the deassertion of the
AVST_READY signal including the delay incurred by the 2-stage register
synchronizer.
•
The host must synchronize the AVST_READY signal to the AVST_CLK signal using
a 2-stage register synchronizer. Here is Register transfer level (RTL) example code
for 2-stage register synchronizer:
always @(posedge avst_clk or negedge reset_n)
begin
if (~reset_n)
begin
fpga_avst_ready_reg1 <= 0;
fpga_avst_ready_reg2 <= 0;
else
fpga_avst_ready_reg1 <= fpga_avst_ready;
fpga_avst_ready_reg2 <= fpga_avst_ready_reg1;
end
end
Where:
—
The AVST_CLK signal comes from either PFL II IP or your Avalon-ST controller
logic.
—
fpga_avst_ready is the AVST_READY signal from the Intel Stratix 10 device
—
fpga_avst_ready_reg2 signal is the AVST_READY signal that is
synchronous to AVST_CLK.
You must properly constrain the AVST_CLK and AVST_DATA signals at the host.
Perform timing analysis on both signals between the host and Intel Stratix 10 device
to ensure the Avalon-ST configuration timing specifications are met. Refer to the
Avalon-ST Configuration Timing section of the Intel Stratix 10 Device Datasheet for
information about the timing specifications.
Note:
The AVST_CLK signal must run continuously during configuration. The AVST_READY
signal cannot assert unless the clock is running.
Optionally, you can monitor the CONF_DONE signal to indicate the flash has sent all the
data to FPGA or to indicate the configuration process is complete.
If you use the PFL II IP core as the configuration host, you can use the Intel Quartus
Prime software to store the binary configuration data to the flash memory through the
PFL II IP core.
If you use the Avalon-ST Adapter IP core as part of the configuration host, set the
Ready Latency value between 1- 6.
Avalon-ST x8 configuration scheme uses the SDM pins only. Avalon-ST x16 and x32
configuration scheme additionally use dual-purpose I/O pins that you can use as
general-purpose IO pins after configuration.
Related Information
• Avalon-ST Configuration Timing in Intel Stratix 10 Device Datasheet
• Avalon Interface Specifications
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
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Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English