Intel Stratix 10 Configuration User Guide

The numbers in the Initial Configuration part of the timing diagram mark the following
events:
1.
The SDM boots up and samples the MSEL signals to determine the specified FPGA
configuration scheme. The SDM does not sample the MSEL pins again until the
next power cycle.
2.
With the nCONFIG signal low, the SDM enters Idle mode after booting.
3.
When the external host drives nCONFIG signal high, the SDM initiates
configuration. The SDM drives the nSTATUS signal high, signaling the beginning of
FPGA configuration. The SDM receives the configuration bitstream on the interface
that MSEL value sampled in Step 1.
4.
The SDM drives the CONF_DONE signal high, indicating successful configuration.
5.
When the Intel Stratix 10 device asserts INIT_DONE the FPGA enters user mode.
GPIO pins exit the high impedance state. The entire device does not enter user
mode at the same instant.
Reconfiguration Timing
The second event the timing diagram illustrates the Intel Stratix 10 device
reconfiguration. Note that the reconfiguration assumes that you have not changed the
MSEL setting. If you do change the MSEL setting after power-on, you must power-
cycle the Intel Stratix 10 device. Power cycling forces the SDM to sample the MSEL
pins before reconfiguring the device.
The numbers in the Reconfiguration part of the timing diagram mark the following
events:
1.
The external host drives nCONFIG signal low.
2. The SDM initiates device cleaning.
3.
The SDM drives the nSTATUS signal low when device cleaning is complete.
4.
The external host drives the nCONFIG signal high to initiate reconfiguration.
5.
The SDM drives the nSTATUS signal high signaling the device is ready for
reconfiguration.
Configuration Error
The numbers in the Configuration Error part of the timing diagram mark the following
events:
1.
The SDM drives nSTATUS signal low for 1 ms ±50% to indicate a
configuration error. The Intel Stratix 10 devices does not assert
CONF_DONE indicating that configuration did not complete successfully.
2. The SDM enters the error state.
3.
The SDM enters the idle state. The external host deasserts nCONFIG. The device
is ready for reconfiguration by driving a low to high transition on nCONFIG. You
can also power cycling the device by following the device power down sequence.
2. Intel Stratix 10 Configuration Details
UG-S10CONFIG | 2018.11.02
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Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English