Intel Stratix 10 Configuration User Guide

Configuration Scheme Data Width (bits) MSEL[2:0]
Active
SD MMC 4/8 100
AS - fast mode 4 001
AS - normal mode 4 011
Avalon-ST
The Avalon-ST configuration scheme is a new passive configuration scheme for Intel
Stratix 10 devices. It replaces the fast passive parallel (FPP) mode available in earlier
device families. Avalon-ST is the fastest configuration scheme for Intel Stratix 10
devices. Avalon-ST configuration supports x8, x16, and x32 modes. The x16 and x32
bit modes use general-purpose I/Os (GPIOs) for configuration. You can repurpose
these GPIOs after configuration completes. The x8 bit mode uses dedicated SDM I/O
pins.
Avalon-ST differs from FPP configuration in supporting backpressure using the
AVST_READY and AVST_VALID pins. Because the time to decompress the incoming
bitstream varies, backpressure support is necessary to transfer data to the Intel
Stratix 10 device. For more information about the Avalon-ST refer to the Avalon
Interface Specifications.
JTAG
You can configure the Intel Stratix 10 device using the dedicated JTAG pins. The JTAG
port provides seamless access to many useful tools and functions. In addition to
programming memories JTAG port is useful for debugging using Signal Tap or the
System Console tools.
The JTAG port has the highest priority and overrides the MSEL pin settings.
Consequently, you can configure the Intel Stratix 10 device over JTAG even if the
MSEL pin specifies a different configuration scheme unless you disabled JTAG for
security reasons.
CvP
CvP uses an external PCIe* host device as a Root Port to configure the Intel Stratix 10
device over the PCIe link. You can specify up to a x16 PCIe link. Intel Stratix 10
devices support two CvP modes, CvP init and CvP update.
CvP initialization process includes the following two steps:
1. CvP configures the FPGA periphery image which includes I/O information and hard
IP blocks, including the PCIe IP. Because the PCIe IP is in the periphery image,
PCIe link training establishes PCIe link of the CvP PCIe IP before the core fabric
configures.
2. Then, the host device uses the CvP PCIe link to configure your design in the core
fabric.
1. Intel
®
Stratix
®
10 Configuration Overview
UG-S10CONFIG | 2018.11.02
Send Feedback
Intel Stratix 10 Configuration User Guide
5

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English