Figure 32. Connection Setup for JTAG Single-Device Configuration using Download Cable
Intel® Stratix®10
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
TCK
TDO
TDI
TMS
Configuration
Control Signals
JTAG
Configuration
Pins
Optional
Monitoring
To JTAG
Header or
JTAG Chain
10kΩ
MSEL
V
CCIO_SDM
3
Pin 1
Download cable 10 pin male header (JTAG mode)
R
UP
R
DN
R
UP
TCK
TDO
TMS
OPEN
TDI
GND
VCCIO_SDM
OPEN
OPEN
GND
G
ND
V
CCIO_SDM
Related Information
• Intel FPGA Download Cable II User Guide
• Intel Stratix 10 Device Family Pin Connection Guidelines
3.4.1.2. JTAG Single-Device Configuration using a Microprocessor
Refer to the Intel Stratix 10 Device Family Pin Connection Guidelines for additional
information about individual pin usage and requirements.
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
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Intel Stratix 10 Configuration User Guide
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