LUMENIS VersaPulse PowerSuite - 4.4.2.1 Digital I;O Circuits

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SPKR - A speaker signal is asserted by the timer to the audio amp driver circuit each time the laser is
fired or a user input is detected.
SAFE_ERR_IRQ - A safety error IRQ interrupt signal from the Safety Control Logic EPLD U40.
U55 displays the various error codes and condition the microprocessor is in. The four conditions are:
Service Mode
RAM check
Standby
Ready
SW2 sets the system into service mode. Sliding SW2 inputs a /SERVICE/ signal to the Digital Input/Output
EPLD U49 causing the microprocessor to go into service mode.
SW3 sets the system into autocalibration mode. Sliding SW3 to the left inputs an AUTO_CAL signal to the
Digital Input/Output EPLD U49.
SW4 sets the service attenuator switch. Sliding SW4 inputs a /SERVICE_ATTEN_SW/ signal to the Digital
Input/Output EPLD U49, resulting in placing the service attenuator into the beam path.
4.4.2.1 Digital I/O Circuits
Refer to page 8-9 in Section 8. The microprocessor uses digital I/Os to read in high or low logic levels from
throughout the system. In this manner, the microprocessor can check the condition of various circuits, sensors
and etc.
The EPLD inputs and outputs are programmable and in the VersaPulse PowerSuite is used to serve in multiple
functions in the system due to the flexibility of this chip. The Digital Input/Output EPLD U49 serves as an 8-
channel digital I/O for the microprocessor. The EPLD can output high or low levels to control devices such as
the high voltage power supply, integrated circuits and etc.
The EPLD used for digital I/O consists of two logically independent sections; the ports and timer. The port
section consists of 8 channels with 10 ports each which are bi-directional. It can output signals as well as
receive input signals. There are two inputs on the EPLD to receive clock input signals (GCLK1, GCLK2).