MEDIATEK Ralink MT7620 - Page 157

PGMT7620_V.1.0_040503
Page 157 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
3
RW
TX_INT3_EN
INT_STATUS[3] Enable
Enables the Tx DMA Fault Detected Interrupt.
This interrupt asserts when a fault is detected
in Tx DMA signals.
0x0
2
RW
TX_INT2_EN
INT_STATUS[2] Enable
Enables the Tx FIFO Overrun Interrupt. This
interrupt asserts when the Tx FIFO is overrun.
0x0
1
RW
TX_INT1_EN
INT_STATUS[1] Enable
Enables the Tx FIFO Underrun Interrupt. This
interrupt asserts when the Tx FIFO is underrun.
0x0
0
RW
TX_INT0_EN
INT_STATUS[0] Enable
Enables the Tx FIFO Below Threshold Interrupt.
This interrupt asserts when the FIFO is lower
than the defined threshold.
0x0
NOTE:
0: Disable
1: Enable
194. FF_STATUS: I
2
S Tx/Rx FIFO Status (offset: 0x000C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:4
RO
RX_AVCNT
Rx FIFO Available Space Count
Counts the available space for reads in Rx FIFO.
(unit: word)
0x0
3:0
RO
TX_EPCNT
Tx FIFO Available Space Count
Counts the available space for writes in Tx FIFO.
(unit: word)
0x8
195. TX_FIFO_WREG: Tx Write Data Buffer (offset: 0x0010)
Bits
Type
Name
Description
Initial Value
31:0
WO
TX_FIFO_WDATA
Tx FIFO Write Data Buffer
Buffers data to be written to the Tx FIFO.
0x0
196. RX_FIFO_RREG: Rx Read Data Buffer (offset: 0x0014)
Bits
Type
Name
Description
Initial Value
31:0
RO
RX_FIFO_RDATA
Rx FIFO Read Data Buffer
Buffers data read from the Rx FIFO.
0x0
197. I2S_CFG1: I
2
S Loopback Test Control Register (offset: 0x0018)
Bits
Type
Name
Description
Initial Value
31
RW
LBK_EN
Enables loopback mode.
0: Normal mode
1: Loopback mode
ASYNC_TXFIFIO  Tx  Rx  ASYNC_RXFIFIO
0x0