MEDIATEK Ralink MT7620 - Page 158

PGMT7620_V.1.0_040503
Page 158 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
30
RW
EXT_LBK_EN
Enables external loopback.
0: Normal mode
1: Enables external loop back.
External A/D  Rx  Tx  External D/A
0x0
29:0
-
-
Reserved
0x0
198. DIVCOMP_CFG: Integer Part of Dividor Register (offset: 0x0020)
Bits
Type
Name
Description
Initial Value
31
RW
CLK_EN
Enables setting of the I
2
S clock based on
DIVCOMP and DIVINT parameters.
0: Disable
1: Enable
0x0
30:9
-
-
Reserved
0x0
8:0
RW
DIVCOMP
A parameter in an equation which determines
FREQOUT. See DIVINT_CFG.
0x0
199. DIVINT_CFG: Integer Part of Dividor Register (offset: 0x0024)
Bits
Type
Name
Description
Initial Value
31:10
-
-
Reserved
0x0
9:0
RW
DIVINT
Integer Divider
A parameter in an equation which determines
FREQOUT:
FREQOUT = FREQIN *(1/2) *
{1 / [DIVINT+DIVCOMP/(512)]}
FREQIN is always fixed to 40 MHz.
0x0