MEDIATEK Ralink MT7620 - Page 200

PGMT7620_V.1.0_040503
Page 200 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
16
R/
W1C
RX_DONE_INT0
Rx Queue 0 Done Interrupt
Asserts when an Rx packet is received on
Queue 0.
0
15:2
-
-
Reserved
-
1
R/
W1C
TX_DONE_INT1
Tx Queue 1 Done Interrupt
Asserts when a Tx Queue 1 packet is
transmitted.
0
0
R/
W1C
TX_DONE_INT0
Tx Queue 0 Done Interrupt
Asserts when a Tx Queue 0 packet is
transmitted.
0
NOTE:
Read:
0: Interrupt not asserted.
1: Interrupt asserted
Write
1: Clear the interrupt
240. INT_MASK: (offset: 0x1228)
Bits
Type
Name
Description
Initial Value
31
RW
RX_COHERENT
_INT_MSK
Masks the Rx Coherent interrupt. This interrupt
asserts when the Rx DMA is ready to handle a
queue, but cannot access the queue because
the driver is not ready.
0
30
RW
RX_ DLY_INT_MSK
Masks the Rx Delay interrupt. This interrupt
asserts when the number of pending Rx
interrupts has reached a specified level, or
when the pending time is reached.
0
29
RW
TX_COHERENT
_INT_MSK
Masks the Tx Coherent interrupt. This interrupt
asserts when the Tx DMA is ready to handle a
queue, but cannot access the queue because
the driver is not ready.
0
28
RW
TX_DLY_INT_MSK
Masks the Tx Delay interrupt. This interrupt
asserts when the number of pending Tx
interrupts has reached a specified level, or
when the pending time is reached.
0
27
RW
MCU_CMD_INT3_MSK
MCU command interrupt 3 enable: Reserved
0
26
RW
MCU_CMD_INT2_MSK
MCU command interrupt 2 enable: Reserved
0
25
RW
MCU_CMD_INT1_MSK
MCU command interrupt 1 enable: Reserved
0
24
RW
MCU_CMD_INT0_MSK
MCU command interrupt 0 enable: Reserved
0
23:18
-
-
Reserved
-
17
RW
RX_DONE_INT_MSK1
Masks the Rx Queue 1 Done interrupt. This
interrupt asserts when an Rx packet is received
on Queue 1.
0
16
RW
RX_DONE_INT_MSK0
Masks the Rx Queue 0 Done interrupt. This
interrupt asserts when an Rx packet is received
on Queue 0.
0