MEDIATEK Ralink MT7620 - Page 215

PGMT7620_V.1.0_040503
Page 215 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
15:12
RW
LAN_TR3_FCON
PDMA Tx Ring #3 Flow Control by LAN port of
the switch
Selects when to pause Tx ring #3.
Bit[19]: When GSW LAN Q3 is full.
Bit[18]: When GSW LAN Q2 is full.
Bit[17]: When GSW LAN Q1 is full.
Bit[16]: When GSW LAN Q0 is full.
0xF
11:8
RW
LAN_TR2_FCON
PDMA Tx Ring #2 Flow Control by LAN port of
the switch
Selects when to pause Tx ring #2.
Bit[19]: When GSW LAN Q3 is full.
Bit[18]: When GSW LAN Q2 is full.
Bit[17]: When GSW LAN Q1 is full.
Bit[16]: When GSW LAN Q0 is full.
0xF
7:4
RW
LAN_TR1_FCON
PDMA Tx Ring #1 Flow Control by LAN port of
the switch
Selects when to pause Tx ring #1.
Bit[19]: When GSW LAN Q3 is full.
Bit[18]: When GSW LAN Q2 is full.
Bit[17]: When GSW LAN Q1 is full.
Bit[16]: When GSW LAN Q0 is full.
0xF
3:0
RW
LAN_TR0_FCON
PDMA Tx Ring #0 Flow Control by LAN port of
the switch
Selects when to pause Tx ring #0.
Bit[19]: When GSW LAN Q3 is full.
Bit[18]: When GSW LAN Q2 is full.
Bit[17]: When GSW LAN Q1 is full.
Bit[16]: When GSW LAN Q0 is full.
0xF
248. P2G_FC: PDMA to GSW Flow Control (offset: 0x001C)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0
15:8
RW
RR1_GSW_FCON
PDMA Rx Ring #1 Pause GSW CPU Queue
Selects which GSW queue to pause when PDMA
Rx ring 1 is almost full.
Bit[0]: Queue 0
…
Bit[7]: Queue 7
0x0
7:0
RW
RR0_GSW_FCON
PDMA Rx Ring #0 Pause GSW CPU Queue
Selects which GSW queue to pause when PDMA
Rx ring 0 is almost full.
Bit[0]: Queue 0
…
Bit[7]: Queue 7
0x0