MEDIATEK Ralink MT7620 - Page 22

PGMT7620_V.1.0_040503
Page 22 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
13:12
RW
GE1_MODE
Gigabit Port #1 Mode
Sets the interface mode on Gigabit port 1.
2’b00: RGMII Mode (10/100/1000 Mbps)
2’b01: MII Mode (10/100 Mbps)
2’b10: Reverse MII Mode (10/100 Mbps)
2’b11: Reserved
0x0
11
-
-
Reserved
0x0
10
RW
USB0_HOST_MODE
0: Set USB #0 to device mode
1: Set USB #0 to host mode.
BS
9
-
-
Reserved
0x0
8
RW
PCIE_RC_MODE
0: Set PCIe to EP mode
1: Set PCIe to RC mode
BS
7:4
-
-
Reserved
0x0
3:2
RW
GE2_PIN_DRV
RGMII2 Pin Driving Setting
[1:0]
LVTTL (3.3 V)
LVCMOS (2.5 V)
0
N/A
10 mA
1
N/A
8 mA
2
16 mA
4 mA
3
(8 mA)
(2 mA)
0x3
1:0
RW
GE1_PIN_DRV
RGMII1 Pin Driving Setting
[1:0]
LVTTL (3.3 V)
LVCMOS (2.5 V)
0
N/A
10 mA
1
N/A
8 mA
2
16 mA
4 mA
3
(8 mA)
(2 mA)
0x3
NOTE:
1. For bits marked with an *, the default value is defined by bootstrap “DRAM_TYPE” and can be modified by
software.
2. Default values are marked with parentheses.
6. TESTSTAT: Firmware Test Status Register (offset: 0x0018)
Bits
Type
Name
Description
Initial Value
31:0
RW
TSETSTAT
Firmware Test Status
0x0
NOTE: This register is reset only by a power-on reset.
7. TESTSTAT2: Firmware Test Status Register 2 (offset: 0x001C)
Bits
Type
Name
Description
Initial Value
31:0
RW
TSETSTAT2
Firmware Test Status 2
0x0
NOTE: This register is reset only by a power-on reset.
8. Reserved (offset: 0x0020)
Bits
Type
Name
Description
Initial Value