MEDIATEK Ralink MT7620 - Page 23

PGMT7620_V.1.0_040503
Page 23 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
31:0
RW
BOOTSRAM_BASE
Boot from SRAM base address (Test mode only)
Addr_tuned =
bootsram[31:0] | oc_maddr[15:0]
0x10240000
9. Reserved (offset: 0x0024)
Bits
Type
Name
Description
Initial Value
31:0
-
-
Reserved
0x0
10. Reserved (offset: 0x0028)
Bits
Type
Name
Description
Initial Value
31:0
-
-
Reserved
0x0
11. CLKCFG0: Clock Configuration Register 0 (offset: 0x002C)
Bits
Type
Name
Description
Initial Value
31:30
RW
SDRAM_CLK_SKEW
SDRAM Clock Skew
0: Zero delay
1: Delay 200 ps
2: Delay 400 ps
3: Delay 600 ps
0x1
29:24
RW
OSC_1US_DIV
Oscillator 1 μs Divider
Sets the maximum for the reference clock
counter for either a 20 MHz or 40 MHz external
XTAL input. The count increments each 1 μsec
(indicating 1 MHz), up to the maximum, before
resetting to zero. This counts the frequency of
an external XTAL. This count is used to output a
32 KHz frequency to the REFCLK0 pin.
6’b0: Automatically generates a 1 μs system tick
regardless of whether XTAL frequency is 20
MHz or 40 MHz.
6’d39: Default value for an external 40 MHz
XTAL.
6’d19: Default value for an external 20 MHz
XTAL.
Others: Manual mode for tick generation.
0x0
23
-
-
Reserved
0x0
22:18
RW
INT_CLK_FDIV
Internal Clock Frequency Divider
The frequency divider used to generate the
Fraction-N clock frequency.
Valid values range from 1 to 31.
Fraction-N clock frequency =
(INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
0x8
17
-
-
Reserved
0x0