MEDIATEK Ralink MT7620 - Page 24

PGMT7620_V.1.0_040503
Page 24 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
16:12
RW
INT_CLK_FFRAC
Internal Clock Fraction-N Frequency
A parameter used in conjunction with
INT_CLK_FDIV to generate the Fraction-N clock
frequency.
Valid values range from 0 to 31.
Fraction-N clock Frequency =
(INT_CLK_FFRAC/INT_CLK_FDIV)*PLL_FREQ
0x0
11:9
RW
REFCLK0_RATE
Reference Clock 0 Rate
0: Xtal clock 20/40 MHz
1: 12 MHz
2: 25 MHz
3: 40 MHz
4: 48 MHz
5: Internal Fraction-N_CLK/2
6: Reserved
7: CPLL_DIV8
0x0
8
-
-
Reserved
0x0
7:5
-
-
Reserved
0x0
4
RW
PERI_CLK_SEL
Peripheral Clock Source Select
Sets the peripheral clock to use the 20/40 MHz
frequency input from XTAL.
0: 40 MHz from 480 MHz divided by 12.
1: 20 MHz/40M Hz from XTAL input
0x0
3
RW
EPHY_USE_25M
EPHY Clock Source Select
Set the EPHY clock to use the 25 MHz frequency
input from the PPLL.
0: EPHY use 20/40 MHz from XTAL
1: EPHY use 25 MHz from PPLL
0x0
2
-
-
Reserved
0x0
1:0
-
-
Reserved
0x0
12. CLKCFG1: Clock Configuration Register 1 (offset: 0x0030)
Bits
Type
Name
Description
Initial Value
31
-
-
Reserved
0x0
30
RW
SDHC_CLK_EN
SDHC clock enable
0x1
29
-
-
Reserved
0x1
28
RW
AUX_STCK_ CLK_EN
Aux system tick clock enable
0x1
27
-
-
Reserved
0x0
26
RW
PCIE0_ CLK_EN
PCIE0 clock enable
0x1
25
RW
UPHY0_ CLK_EN
UPHY0 clock enable
0x1
24
-
-
Reserved
0x1
23
RW
ESW_ CLK_EN
Ethernet switch clock enable
0x1