MEDIATEK Ralink MT7620 - Page 25

PGMT7620_V.1.0_040503
Page 25 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
22
-
-
Reserved
0x1
21
RW
FE_ CLK_EN
FE clock enable
0x1
20
-
-
Reserved
0x0
19
RW
UARTL_ CLK_EN
UART Lite clock enable
0x1
18
RW
SPI CLK_EN
SPI clock enable
0x1
17
RW
I2S CLK_EN
I2S clock enable
0x1
16
RW
I2C CLK_EN
I2C clock enable
0x1
15
RW
NAND_CLK_EN
Nand flash control clock enable
0x1
14
RW
GDMA CLK_EN
GDMA clock enable
0x1
13
RW
PIO CLK_EN
GPIO controller clock enable
0x1
12
RW
UART_ CLK_EN
UART clock enable
0x1
11
RW
PCM_ CLK_EN
PCM clock enable
0x1
10
RW
MC_ CLK_EN
Memory controller clock enable
0x1
9
RW
INTC_ CLK_EN
Interrupt controller clock enable
0x1
8
RW
TIMER_CLK_EN
Timer clock enable
0x1
7
RW
GE2_CLK_EN
GE2 controller clock enable.
0x1
6
RW
GE1_CLK_EN
GE1 controller clock enable.
0x1
5:0
-
-
Reserved
0x0
NOTE:
0: Clock is gated.
1: Clock is enabled.
13. RSTCTRL: Reset Control Register (offset: 0x0034)
Bits
Type
Name
Description
Initial Value
31
RW
PPE_RST
Resets PPE
0x0
30
RW
SDHC_RST
Resets SD Controller.
0x0
29
-
-
Reserved
0x0
28
RW
MIPS_CNT_RST
Resets MIPS counter block.
0x0
27
-
-
Reserved
0x0
26
RW
PCIE0_RST
Resets PCIE Host Bridge, PCIE0 Controller and
PHY.
0x0
25
RW
UHST0_RST
Resets USB PHY0.
NOTE: USB Host controller will be reset when
both UHST0_RST and UHST1_RST are set.
0x0
24
RW
EPHY_RST
Resets the Ethernet PHY block.
0x0
23
RW
ESW_RST
Resets the Ethernet switch block.
0x0
22
-
-
Reserved
0x0
21
RW
FE_RST
Resets the Frame Engine block.
0x0
20
RW
WLAN_RST-
Resets the WLAN block.
0x0
19
RW
UARTL_RST
Resets the UART Lite block.
0x0