MEDIATEK Ralink MT7620 - Page 26

PGMT7620_V.1.0_040503
Page 26 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
18
RW
SPI
Resets the SPI block.
0x0
17
RW
I2S
Resets the I
2
S block.
0x0
16
RW
I2C
Resets the I
2
C block.
0x0
15
RW
NAND
Resets the NAND block.
0x0
14
RW
DMA
Resets the DMA block.
0x0
13
RW
PIO
Resets the PIO block.
0x0
12
RW
UART_RST
Resets the UART block.
0x0
11
RW
PCM_RST
Resets the PCM block.
0x0
10
RW
MC_RST
Resets the Memory Controller block.
0x1
9
RW
INTC_RST
Resets the Interrupt Controller block.
0x0
8
RW
TIMER_RST
Resets the Timer block.
0x0
7:1
-
-
Reserved
0x0
0
W1C
SYS_RST
Resets the whole SoC.
0x0
NOTE:
0: Deassert reset
1: Reset
14. RSTSTAT: Reset Status Register (offset: 0x0038)
Bits
Type
Name
Description
Initial Value
31
RW
WDT2SYSRST_EN
Watchdog Timeout To System Reset Enable
Enables watchdog timeout to trigger a system
reset.
0: Disable
1: Enable
0x1
30
RW
WDT2RSTO_EN
Watchdog Timeout to Reset Output Enable
Enables watchdog timeout to trigger the reset
output pin.
0: Disable
1: Enable
0x1
29:16
RW
WDTRSTPD
Watchdog Reset Output Low Period
Controls the WDT reset output low period. For
example:
If the pin share mode was set correctly and
WDT2RSTO_EN=1,
 When WDTRSTPD= 0, you can see duration
of 1 μs low on the WDT reset output pin.
 When WDTRSTPD= 3, you can see duration
of 4 μs low on the WDT reset output pin.
(unit: 1 μs)
0x3
15:4
-
-
Reserved
0x0