MEDIATEK Ralink MT7620 - Page 27

PGMT7620_V.1.0_040503
Page 27 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
3
R/W1C
SWCPURST
Software CPU Reset
Indicates when software has reset the CPU by
writing to the RSTCPU bit in RSTCTL.
0: Has no effect.
1: Clears this bit.
NOTE: This register is reset only by a power-on
reset.
0x0
2
R/W1C
SWSYSRST
Software System Reset
Indicates when software has reset the chip by
writing to the RSTSYS bit in RSTCTL.
0: Has no effect.
1: Clears this bit.
NOTE: This register is reset only by a power on
reset.
0x0
1
R/W1C
WDRST
Watchdog Reset
Indicates when the watchdog timer has reset
the chip.
0: Has no effect.
1: Clears this bit.
NOTE: This register is reset only by power-on
reset.
0x0
0
-
-
Reserved
0x0
15. CPU_SYS_CLKCFG: CPU and SYS Clock Control (offset: 0x003C)
Bits
Type
Name
Description
Initial Value
31:20
-
-
Reserved
0x0
19:16
RW
CPU_OCP_RATIO
CPU OCP Ratio
The ratio between the system bus frequency
and the CPU frequency.
Value
Ratio (SYS : CPU )
4’d0
1 : 1 (Reserved)
4’d1
1 : 1.5 (Reserved)
4’d2
1 : 2
4’d3
1 : 2.5 (Reserved)
4’d4
1 : 3
4’d5
1 : 3.5 (Reserved)
4’d6
1 : 4
4’d7
1 : 5
4’d8
1 : 10
Others
Reserved
NOTE: If the chip runs in USB OHCI mode, the
OCP frequency cannot be lower than 30 MHz. It
means that
PLL_FREQ*(CPU_FFRAC/CPU_FDIV)/(CPU_OCP_
RATIO+1) >= 30 MHz.
0x4
15:13
-
-
Reserved
0x0