MEDIATEK Ralink MT7620 - Page 28

PGMT7620_V.1.0_040503
Page 28 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
12:8
RW
CPU_FDIV
CPU Frequency Divider
The frequency divider is used to generate the
CPU frequency. The value must be larger than
or equal to CPU_FFRAC. Valid values range from
1 to 31.
0xA
7:5
-
-
Reserved
0x0
4:0
RW
CPU_FFRAC
CPU Frequency Fractional
A parameter used in conjunction with the CPU
frequency divider to determine the CPU
frequency. Input a value in the following
equation to determine the CPU frequency.
Valid values range from 0 to 31.
CPU frequency =
(CPU_FFRAC/CPU_FDIV)*PLL_FREQ
NOTE: If the chip runs in USB OHCI mode, the
OCP frequency cannot be lower than 30 MHz. It
means that
PLL_FREQ*(CPU_FFRAC/CPU_FDIV)/(CPU_OCP_
RATIO+1) >= 30 MHz.
0x1
NOTE:
1. Equation used to derive system frequency after chip boot up:
PLL_FREQ = 600
CPU_FREQ = PLL_FREQ * (CPU_FFRAC / CPU_FDIV).
BUS_FREQ = CPU_FREQ/3. (CPU_OCP_RATIO = 1:3)
Limitations:
CPU_FDIV >= CPU_FFRAC.
2. If the chip runs the USB function, the OCP frequency cannot be lower than 30 MHz. Then PLL_FREQ
follows this limitation.
BUS_FREQ >= 30 MHz.
3. Example:
PLL_FREQ = 600 MHz.
CPU_FREQ = 600 * (1/5) = 300 MHz. (CPU_FFRAC=1; CPU_FDIV=5)
BUS_FREQ = 300/3 = 100 MHz. (CPU_OCP_RATIO=1:3)