MEDIATEK Ralink MT7620 - Page 29

PGMT7620_V.1.0_040503
Page 29 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
16. CLK_LUT_CFG: CPU and SYS Clock Auto Control (offset: 0x0040)
Bits
Type
Name
Description
Initial Value
31
RW
SLP_EN
Sleep Mode Enable
Enables sleep mode when MIPS SI_Sleep is
asserted.
0: Disable
1: Enable
Sleep Mode CPU Frequency =
(1/CPU_FDIV)*PLL_FREQ
0x0
30
RW
STEP_EN
Step Jump Enable
Enables step jump after MIPS exits sleep mode.
The CPU will jump to the normal frequency in
increments defined by STEP_FFRAC.bit[4:0] of
this register.
0: Disable
1: Enable
0x0
29:28
-
-
Reserved
0x0
27:20
RW
STEP_CNT
Step Counter
Sets the period of each step jump. When the
counter counts down to zero, the CPU clock
automatically changes to the next step
frequency.
The count period unit is 1 μs.
0x2
19:16
RW
SLP_OCP_RATIO
Sleep Mode CPU and System Bus Frequency
Ratio
Sets the ratio between the system bus frequency
and the CPU frequency when entering sleep
mode. (SYS:CPU)
Value
Ratio (SYS : CPU )
4’d0
1 : 1
4’d1
1 : 1.5 (Reserved)
4’d2
1 : 2
4’d3
1 : 2.5 (Reserved)
4’d4
1 : 3
4’d5
1 : 3.5 (Reserved)
4’d6
1 : 4
4’d7
1 : 5
4’d8
1 : 10
Others
Reserved
0x4
15:5
-
-
Reserved
0x0