MEDIATEK Ralink MT7620 - Page 30

PGMT7620_V.1.0_040503
Page 30 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
4:0
RW
STEP_FFRAC
Step Frequency Fraction
Sets the fractional size of the increment in CPU
frequency after the CPU exits from sleep mode
and returns to normal operation. This step is
only valid when SLP_STEP_EN is enabled.
FRAC_VALUE =
PREVIOUS_FRAC_VALUE + STEP_FFRAC
CPU Frequency =
(FRAC_VALUE/CPU_FDIV)*PLL_FREQ
0x6
17. CUR_CLK_STS: Current Clock Status (offset: 0x0044)
Bits
Type
Name
Description
Initial Value
31:21
-
-
Reserved
0x0
20
RO
SAME_FREQ
Indicates that the SYS and DRAM clocks are on
the same frequency.
0: False
1: True
-
19:16
RO
CUR_OCP_RATIO
Current CPU_OCP_Ratio (SYS : CPU)
Shows the current ratio between the system bus
and CPU frequencies.
Value
Ratio (SYS : CPU )
4’d0
1 : 1
4’d1
1 : 1.5 (Reserved)
4’d2
1 : 2
4’d3
1 : 2.5 (Reserved)
4’d4
1 : 3
4’d5
1 : 3.5 (Reserved)
4’d6
1 : 4
4’d7
1 : 5
4’d8
1 : 10
Others
Reserved
-
15:13
-
-
Reserved
0x0
12:8
RO
CUR_CPU_FDIV
Current CPU Frequency Divider
The frequency divider is used to generate the
CPU frequency.
For more information, see CPU_SYS_CLKCFG,
offset 0x003C, bit[12:8].
0xA
7:5
-
-
Reserved
0x0
4:0
RO
CUR_CPU_FFRAC
Current CPU Frequency Fraction
A parameter used in conjunction with the CPU
frequency divider to determine the CPU
frequency.
For more information, see CPU_SYS_CLKCFG,
offset 0x003C, bit[4:0].
0x1