MEDIATEK Ralink MT7620 - Page 31

PGMT7620_V.1.0_040503
Page 31 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
18. BPLL_CFG0: BB PLL Configuration 0 (offset: 0x0048)
Bits
Type
Name
Description
Initial Value
31
RW
BPLL_SW_CFG
BB PLL Software Configuration
Sets BB PLL parameters set by software.
0: Apply default parameters set by hardware.
1: Apply new parameters set by software in
BPLL_CFG0 & BPLL_CFG1.
0x0
30:23
-
-
Reserved
0x0
22:20
RW
BBPL_OPTION
Reserved
0x0
19:17
-
-
Reserved
0x0
16
RW
BBPL_PD
BB PLL Power Down
0: Power On
1: Power Down
0x0
15:14
-
-
Reserved
0x0
13
RO
BBPL_FBDV2
BB PLL Feedback Divisor 2
This value depends on the bootstrap pin.
<0x0>: 40 MHz
<0x1>: 20 MHz
BS
12
RW
BBPL_FOUTDV2
BB PLL Frequency Output Divisor 2
0: Fixed at 960 MHz
0x0
11:8
RW
BBPL_RDV
BB PLL Reference Input Divisor
divisor: M=RDV[3:0])
0x1
7:4
RW
BBPL_FDV
BB PLL Feedback Divisor Control
Sets the real feedback divisor (N) based on the
value of BBPL_FBDV2 (bit13).
 If FBDV2=0, N=FDV[3:0]+16
 If FBDV2=1, N=2*(FDV[3:0]+16)
0x8
3:0
RW
BBPL_ODV
FOUT Frequency Control
Sets the real output divisor (P) based on the
value of BBPL_FOUTDIV2 (bit12).
 If FOUTDV2=0, P=ODV[3:0]
 If FOUTDV2=1, P=ODV[3:0]*2
NOTE: In this chip ODV[3:0]=0000, so FOUT=0.
0x1
19. BPLL_CFG1: BB PLL Configuration 0 (offset: 0x004C)
Bits
Type
Name
Description
Initial Value
31
-
-
Reserved
0x0
30
RO
BBPL_OK
Lock-detector state
0: Not locked
1: Locked
-