MEDIATEK Ralink MT7620 - Page 32

PGMT7620_V.1.0_040503
Page 32 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
29:28
RW
BBPL_ICPP
PLL CPP current control
Sets the proportional charge pump current.
(Default: 01)
00: 25 μA
10: 75 μA
01: 50 μA
11: 100 μA
0x1
27:26
RW
BBPL_ICPI
PLL CPI current control
Sets the integral charge pump current.
00: 1.25 μA
10: 3.75 μA
01: 2.5 μA
11: 5 μA
0x1
25:24
RW
BBPL_VCS
PLL I-path initial voltage
00: Reserved
10: 600 mV
01: 500 mV
11: 700 mV
0x2
23
RW
BBPL_BP
PLL bypass mode for testing
0: Normal mode
1: Bypass mode
0x0
22:21
RW
BBPL_TESTSEL
Bandgap output test current selection
01: Pass bandgap PMOS current to output
10: Pass bandgap NMOS current to output
11: Reserved
0x0
20:17
RW
BBPL_OTDV
FTEST frequency control
Sets the FTEST frequency based on the value of
BBPL_FTESTDV2 (bit16).
 If FTESTDV2=0,
divisor=OTDV[3:0], OTDV[3:0]=0001, FTEST=0
 If FTESTDV2=1,
divisor=OTDV[3:0]*2, OTDV[3:0]=0001,
FTEST=0
NOTE: In this chip OTDV[3:0]=0000, so FTEST=0.
0x0
16
RW
BBPL_FTESTDV2
FTEST Divisor 2
Used in bit[20:17] to calculate FTEST frequency.
0x1
15
RW
BBPL_FOKTH
Lock Detection FOUT Threshold Selection
0: Freq. window < +/- 3.2%
1: Disable (BBPL_OK=1)
0x0
14:13
RW
BBPL_TSTT
The time AFC waits until BIAS is ready
00: 5 μs
10: 20 μs
01: 10 μs
11: 40 μs
0x0