MEDIATEK Ralink MT7620 - Page 33

PGMT7620_V.1.0_040503
Page 33 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
12:11
RW
BBPL_TLCK
BB PLL Time Lock
The delay from when AFC is ready to when PLL
starts locking.
00: 5 μs
10: 20 μs
01: 10 μs
11: 40 μs
0x0
10
RW
BBPL_FORCE
Force PLL open loop
0: Close loop
1: Open loop
0x0
9:0
RW
BBPL_AFC
BB PLL Automatic Frequency Calibration
VCO band selection/output code[8:0]
0xxxxxxxxx: Normal
1xxxxxxxxx: Manual set
When read, BBPL_AFC[8:0] is the output code
from BBPL macro
0x0
20. CPLL_CFG0: CPU PLL Configuration 0 (offset: 0x0054)
Bits
Type
Name
Description
Initial Value
31
RW
CPLL_SW_CFG
CPU PLL Software Configuration
Sets CPU PLL parameters set by software.
0: Apply default parameters set by hardware.
1: Apply new parameters set by software in
CPLL_CFG0[25:0], CPLL_CFG1[9:0] and [26].
0x0
30:25
-
-
Reserved
0x0
24
RW
OPEN_LOOP
Force PLL Open Loop
Forces PLL to operate in open loop mode.
0: Closed loop
1: Open loop
0x0
23:22
RW
AFC_WAIT_TIME
Automatic Frequency Calibration (AFC) Wait
Time
The time AFC waits until BIAS is ready.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs
0x0
21:20
RW
PLL_LOCK_TIME
PLL Lock Time
The delay from when AFC is ready to when PLL
starts locking.
00: 5 μs
01: 10 μs
10: 20 μs
11: 40 μs
0x0