MEDIATEK Ralink MT7620 - Page 34

PGMT7620_V.1.0_040503
Page 34 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
19
RW
EC_CUPLLOK
CPU Lock OK
0: Check AFC. After AFC, if F
vco
is within ± 3.2% of
the target value, this bit is set to 1.
1: Set this bit to always indicate CPU Lock status
is OK, and disable the AFC check.
0x0
18:16
RW
PLL_MULT_RATIO
PLL Multiplying Ratio
Sets the ratio between the VCO and reference
clock frequencies.
 When LC_CURFCK = 0:
Factor=1
PLL_MULT_RATIO =
F
VCO
/ F
REF
(40 MHZ)/ Factor
 When LC_CURFCK = 1:
Factor=2
PLL_MULT_RATIO =
F
VCO
/ F
REF
(20 MHZ)/ Factor
where
F
VCO
= VCO frequency
F
REF
= Reference clock frequency
000: 24
001: 25
010: 26
011: 27
100: 28
101: 29
110: 30 (default)
111: 31 (test only)
0x6
15
RW
LC_CURFCK
PLL Input Frequency Source
0: 40 MHz
1: 20 MHz
BS
14
RW
BYPASS_REF_CLK
Bypass Reference Clock
0: Normal
1: Bypass
0x0
13:12
RW
IPATH_INI_VAL
I-path Initial Voltage
00: Reserved
01: 500 mV
10: 600 mV (default)
11: 700 mV
0x2