MEDIATEK Ralink MT7620 - Page 35

PGMT7620_V.1.0_040503
Page 35 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
11:10
RW
PLL_DIV_RATIO
PLL Dividing Ratio
Sets the ratio between the VCO and PLL output
frequency.
PLL_DIV_RATIO = F
VCO
/F
OUT.
where
F
VCO
= VCO frequency
F
OUT
= PLL output frequency
00: 2 (default)
01: 3
10: 4
11: 8
0x0
9:8
RW
SSC_UP_BOUND
Spread Spectrum Clock (SSC) Frequency Upper
Boundary
00: 0 (default)
01: 1/4 SSC swing
10: 2/4 SSC swing
11: 3/4 SSC swing
0x0
7
RW
SSC_EN
Spread Spectrum Clock (SSC) Enable
Enables the spread spectrum clock (SSC) to
reduce EMI and improve SNR.
0: Disable (default)
1: Enable
0x0
6:4
RW
SSC_SWING
SSC Swing
000: 1250 ppm
001: 2500 ppm
010: 3750 ppm
011: 5000 ppm
100: 6250 ppm
101: 7500 ppm
110: 8750 ppm
111: 10000 ppm (default)
0x7
3:2
RW
INT_PATH_OPT
Integration Path Option
00: 1.25 μA (default)
01: 2.5 μA
10: 3.75 μA
11: 5 μA
0x0
1:0
RW
PRO_PATH_OPT
Proportional Path Option
00: 25 μA
01: 50 μA (default)
10: 75 μA
11: 100 μA
0x1