MEDIATEK Ralink MT7620 - Page 36

PGMT7620_V.1.0_040503
Page 36 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
21. CPLL_CFG1: CPU PLL Configuration 1 (offset: 0x0058)
Bits
Type
Name
Description
Initial Value
31:27
-
-
Reserved
0x0
26
RW
CPLL_PD
CPU PLL Power Down
0: Power on
1: Power down
0x0
25
RW
CPU_CLK_AUX1
CPU Clock Source Select
Selects CPU source clock from aux0 or Xtal_IN
pins.
0: From aux0
1: From Xtal_IN
0x0
24
RW
CPU_CLK_AUX0
CPU Clock Auxiliary 0 Enable
Selects CPU source clock from temporary 480
Mhz clock.
0: Disable
1: Enable
0x0
23
RO
CPLL_LD
CPLL Lock
0: Unlock
1: Lock
-
22:14
RO
EC_CUAFCOUT
CPU PLL AFC output code
0x0
13:10
RO
EC_CUPHDRFT
SSCG output code
(two’s complement)
0x0
9:0
RW
FR_CUAFCSET
CPU PLL AFC Set
0xxxxxxxxx: Normal
1xxxxxxxxx: Manual set
0x0
22. USB_PHY_CFG: USB PHY Control (offset: 0x005C)
Bits
Type
Name
Description
Initial Value
31:2
-
-
Reserved
0x0
1
RW
UTMI_8B60M
USB UTMI 8-bit 60 Mhz Mode Select
Sets the operation mode of the UTMI interface.
0: 16-bit 30 Mhz mode
1: 8-bit 60 Mhz mode
0x0
0
RW
UDEV_WAKEUP
USB Device Wakeup
Enables remote wakeup of the USB device.
0: Disable
1: Enable
0x0
23. GPIOMODE: GPIO Purpose Select (offset: 0x0060)
Bits
Type
Name
Description
Initial Value