MEDIATEK Ralink MT7620 - Page 266

PGMT7620_V.1.0_040503
Page 266 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
299. RGAC2: REV_03 and REV_0E Control Register (offset: 0x002C)
Bits
Type
Name
Description
Initial Value
31:28
-
-
Reserved
0x0
27
RW
R0E_MANG_FR
REV_0E as Management Frame
1’b0: Disable
1’b1: Regarded as management frame
0x1
26
RW
R0E_PAE_FR
REV_0E as PAE Frame
1’b0: Disable
1’b1: Regarded as PAE frame
0x0
25
RW
R0E_BPDU_FR
REV_0E as BPDU Frame
1’b0: Disable
1’b1: Regarded as BPDU frame
0x0
24:22
RW
R0E_EG_TAG
REV_0E Egress VLAN Tag Attribution
3’b000: System default (disabled)
3’b001: Consistent
3’b010, 3’b011: Reserved
3’b100: Untagged
3’b101: Swap
3’b110: Tagged
3’b111: Stack
0x0
21
RW
R0E_LKY_VLAN
REV_0E Leaky VLAN Enable
1’b1: Enable
1’b0: Disable
0x0
20
RW
R0E_PRI_HIGH
REV_0E Force the Highest Priority
1’b1: Assigned to the highest priority queue
1’b0: System default
0x1
19
RW
R0E_MIR
REV_0E to Mirror Port
1’b0: Disable
1’b1: Frame copied to Mirror port
0x0
18:16
RW
R0E_PORT_FW
REV_0E TO_CPU Forwarding
3’b0xx: System default (disable)
3’b100: System default and CPU port excluded
3’b101: System default and CPU port included
3’b110: CPU port only (As long as the ingress
port is not the CPU port. If the ingress port
is the CPU port, then the system default and
CPU port are excluded.)
3’b111: Frame dropped
0x0
15:12
-
Reserved
0x0
11
RW
R03_MANG_FR
REV_03 as Management Frame
1’b0: Disable
1’b1: Regarded as management frame
0x1
10
RW
R03_BPDU_FR
REV_03 as PAE Frame
1’b0: Disable
1’b1: Regarded as PAE frame
0x0