MEDIATEK Ralink MT7620 - Page 265

PGMT7620_V.1.0_040503
Page 265 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
18:16
RW
R02_PORT_FW
REV_02 TO_CPU Forwarding
3’b0xx: System default (disabled)
3’b100: System default and CPU port excluded
3’b101: System default and CPU port included
3’b110: CPU port only (As long as the ingress
port is not the CPU port. If the ingress port
is the CPU port, then the system default and
CPU port are excluded.)
3’b111: Frame dropped
0x0
15:12
-
-
Reserved
0x0
11
RW
R01_MANG_FR
REV_01 as Management Frame
1’b0: Disable
1’b1: Regarded as management frame
0x1
10
RW
R01_PAE_FR
REV_01 as PAE Frame
1’b0: Disable
1’b1: Regarded as PAE frame
0x0
9
RW
R01_BPDU_FR
REV_01 as BPDU Frame
1’b0: Disable
1’b1: Regarded as BPDU frame
0x0
8:6
RW
R01_EG_TAG
REV_01 Egress VLAN Tag Attribution
3’b000: System Default (Disable)
3’b001: Consistent
3’b010, 3’b011: Reserved
3’b100: Untagged
3’b101: Swap
3’b110: Tagged
3’b111: Stack
0x0
5
RW
R01_LKY_VLAN
REV_01 Leaky VLAN Enable
1’b1: Leaky VLAN enable
1’b0: Disable
0x0
4
RW
R01_PRI_HIGH
REV_01 Force the Highest Priority
1’b1: Assigned to the highest priority queue
1’b0: System default
0x1
3
RW
R01_MIR
REV_01 to Mirror Port
1’b0: Disable
1’b1: Frame copied to Mirror port
0x0
2:0
RW
R01_PORT_FW
REV_01 TO_CPU Forwarding
3’b0xx: System default (disabled)
3’b100: System default and CPU port excluded
3’b101: System default and CPU port included
3’b110: CPU port only (As long as the ingress
port is not the CPU port. If the ingress port
is the CPU port, then the system default and
CPU port are excluded.)
3’b111: Frame Dropped
0x0
NOTE: For more information on this register, see Multicast Frames.