MEDIATEK Ralink MT7620 - Page 264

PGMT7620_V.1.0_040503
Page 264 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
2:0
RW
BPDU_PORT_FW
BPDU TO_CPU Forwarding
3’b0xx: System default (disable)
3’b100: System default and CPU port excluded
3’b101: System default and CPU port included
3’b110: CPU port only (As long as the ingress
port is not the CPU port. If the ingress port
is the CPU port, then the system default
and CPU port are excluded.)
3’b111: Frame dropped
0x0
298. RGAC1: REV_01 and REV_02 Control Register (offset: 0x0028)
Bits
Type
Name
Description
Initial Value
31:28
-
-
Reserved
0x0
27
RW
R02_MANG_FR
REV_02 as Management Frame
1’b0: Disable
1’b1: Regarded as management frame
0x1
26
RW
R02_PAE_FR
REV_02 as PAE Frame
1’b0: Disable
1’b1: Regarded as PAE frame
0x0
25
RW
R02_BPDU_FR
REV_02 as BPDU Frame
1’b0: Non-BPDU Frame
1’b1: Regarded as BPDU frame
0x0
24:22
RW
R02_EG_TAG
REV_02 Egress VLAN Tag Attribution
3’b000: System Default (Disable)
3’b001: Consistent
3’b010, 3’b011: Reserved
3’b100: Untagged
3’b101: Swap
3’b110: Tagged
3’b111: Stack
0x0
21
RW
R02_LKY_VLAN
REV_02 Leaky VLAN Enable
1’b1: Leaky VLAN enable
1’b0: Disable
0x0
20
RW
R02_PRI_HIGH
REV_02 Force the Highest Priority
1’b1: Assigned to the highest priority queue
1’b0: System default
0x1
19
RW
R02_MIR
REV_02 to Mirror Port
1’b0: Disable
1’b1: Frame copied to Mirror port
0x0