MEDIATEK Ralink MT7620 - Page 360

PGMT7620_V.1.0_040503
Page 360 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.21.6.2 Register Descriptions
428. PCICFG: PCI Configuration and Status Register (offset: 0x0000)
Bits
Type
Name
Description
Initial Value
31:24
-
-
Reserved
0x0
23:20
RW
P2P_BR_DEVNUM1
Device number setting of Virtual PCI-PCI bridge
#1.
0x1
19:16
RW
P2P_BR_DEVNUM0
Device number setting of Virtual PCI-PCI bridge
#0.
0x0
15:3
-
-
Reserved
-
2
-
-
Reserved
-
1
RW
PCIRST
PCI Reset Control
0: De-assert the PERST_N pin.
1: Assert the PERST_N pin.
This bit is set to 1 at chip reset.
(Available when PCIe Controller in Host mode)
0x1
0
-
-
Reserved
0x0
429. PCIINT: PCI Interrupt After Enable Mask (offset: 0x0008)
Bits
Type
Name
Description
Initial Value
31:22
-
-
Reserved
0x0
21
RO
PCIINT3
PCIe1 Interrupt Input in Host Mode
This bit indicates the PCIe interrupt from PCIe1
slot.
0x0
20
RO
PCIINT2
PCIe0 Interrupt Input in Host Mode
This bit indicates the PCIe interrupt from PCIe0
slot.
0x0
19
-
PCIINT1
Reserved
0x0
18
-
PCIINT0
Reserved
0x0
17:0
-
-
Reserved
0x0
430. PCIENA: PCI Interrupt Enable (offset: 0x000C)
Bits
Type
Name
Description
Initial Value
31:22
-
-
Reserved
0x0
21
RW
PCIINT3
PCIe1 Interrupt Input in RC (Root Complex)
mode
0: Disable PCIe interrupt
1: Enable PCIe interrupt
0x0
20
RW
PCIINT2
PCIe0 Interrupt Input in RC Mode
0: Disable PCIe interrupt
1: Enable PCIe interrupt
0x0
19
-
PCIINT1
Reserved
0x0
18
-
PCIINT0
Reserved
0x0
17:0
-
-
Reserved
0x0