MEDIATEK Ralink MT7620 - Page 366

PGMT7620_V.1.0_040503
Page 366 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
438. PCIE0_IMBASEBAR0: Internal Memory Base address for BAR0 Space of PCIe Controller (offset: 0x0018)
Bits
Type
Name
Description
Initial Value
31:16
RW
IMBASEBAR0
Internal Memory Base address for BAR0
This register is used when CHIP behaves as a
PCI Express RC.
The actual internal memory address being
accessed by an external PCI host can be
obtained from the following formula:
CHIP address begin accessed = (PCI Address –
BAR0) + IMBASEBAR0.
When writing to this register, the related bit
will take effect when the corresponding bit in
BAR0MSK bit is 1 and BAR0ENB is 1.
0x0
15:0
-
-
Reserved
0x0
439. PCIE0_ID: Vendor and Device ID of PCIe Controller (offset: 0x0030)
Bits
Type
Name
Description
Initial Value
31:16
RW
DEVID
Device ID
0x801
15:0
RW
VENID
Vendor ID
0x1814
440. PCIE0_CLASS: Class Code and Revision ID of PCIe Controller (offset: 0x0034)
Bits
Type
Name
Description
Initial Value
31:8
RW
CCODE
Class Code
0xd8000
7:0
RW
REVID
Revision ID
0x1
441. PCIE_SUBID: Sub Vendor and Device ID of PCIe Controller (offset: 0x0038)
Bits
Type
Name
Description
Initial Value
31:16
RW
SUBSYSID
Sub System ID
0x6352
15:0
RW
SUBVENID
Sub Vendor ID
0x1814
This register is valid when PCIE_RC_MODE = 0. See SYSCFG1 (offset: 0x0014).
442. PCIE0_STATUS: PCIe Status Register (offset: 0x0050)
Bits
Type
Name
Description
Initial Value
31:1
-
-
Reserved
0x0
0
RO
PCIE_LINK_UP_ST
PCIe LTSSM Link up indicator
This bit will reflect the PCIe link up status.
Users can use this bit to see if any device is
plugged into the slot.
0x0
443. DLECR: Datalink Layer Error Counter Register (offset: 0x0060)
Bits
Type
Name
Description
Initial Value
31:0
W1C
DLLP_ERR_CNT
Datalink Layer Error Counter
Records how many times a datalink layer error
occurred.
0x0