MEDIATEK Ralink MT7620 - Page 367

PGMT7620_V.1.0_040503
Page 367 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
444. ECRC: Error Counter Register (offset: 0x0064)
Bits
Type
Name
Description
Initial Value
31:0
W1C
ECRC_ERR_CNT
ECRC Error Counter
Records how many times an ECRC error
occurred.
0x0
2.21.8 Memory Windows Registers (base: 0x1015_0000)
445. MEMWINx: PCI Memory Space Access Window (offset: 0x0000_0000)
Bits
Type
Name
Description
Initial Value
31:0
RW
MEMWIN
PCI Memory Space Access Window
Read
Initiates a bus master read access to an external
PCI device’s memory space.
Write
Initiates a bus master write access to an
external PCI device’s memory space.
The address accessed is specified as requested
address (0 if MEMWIN00 is accessed, 4 if
MEMWIN04 is accessed, etc.) plus MEMBASE.
0x0
2.21.9 IO Windows (base: 0x1016_0000)
446. IOWINx: PCI IO Space Access Window (offset: 0x0002_0000)
Bits
Type
Name
Description
Initial Value
31:0
RW
IOWIN
PCI IO Space Access Window
Read
Initiates a bus master read access to an external
PCI device’s IO space.
Write
Initiates a bus master write access to an
external PCI device’s IO space;
The address accessed is specified as requested
address (0 if IOWIN00 is accessed, 4 if IOWIN04
is accessed, etc.) plus IOBASE.
NOTE: This register is only used when the PCI
core is functioning as a master.
0x0