MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Tx Queue 4 Done Interrupt
Asserts when a Tx Queue 4 packet is
transmitted.
Tx Queue 3 Done Interrupt
Asserts when a Tx Queue 3 packet is
transmitted.
Tx Queue 2 Done Interrupt
Asserts when a Tx Queue 2 packet is
transmitted.
Tx Queue 1 Done Interrupt
Asserts when a Tx Queue 1 packet is
transmitted.
Tx Queue 0 Done Interrupt
Asserts when a Tx Queue 0 packet is
transmitted.
Rx Done Interrupt
Asserts when an Rx packet is received.
Tx Delay Interrupt
Asserts when the number of pending Tx
interrupts has reached a specified level, or
when the pending time is reached. Configure
this interrupt using the DELAY_INT_CFG
register.
Tx Delay Interrupt
Asserts when the number of pended Rx
interrupts has reached a specified level, or
when the pending time is reached. Configure
this interrupt using the DELAY_INT_CFG
register.
NOTE:
Read
0: Interrupt not asserted.
1: Interrupt asserted
Write
1: Clear the interrupt
448. INT_MASK: (offset: 0x0204)
Enables the Baseband Radar interrupt. This
interrupt asserts when the BBP has detected
radar tones.
Enables the Tx Coherent interrupt. This
interrupt asserts when the Tx DMA is ready to
handle a queue, but cannot access the queue
because the driver is not ready.