MEDIATEK Ralink MT7620 - Page 5

PGMT7620_V.1.0_040503
Page 5 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.17.5 OHCI OPERATION REGISTERS (BASE: 0X101C.1000) 185
2.18 USB DEVICE CONTROLLER 186
2.18.1 FEATURES 186
2.18.2 BLOCK DIAGRAM 186
2.18.3 BULK OUT 186
2.18.4 LEGACY MODE 187
2.18.5 AGGREGATION MODE 187
2.18.6 DE-AGGREGATION MODE 188
2.18.7 BULK-OUT AGGREGATION FORMAT 189
2.18.8 BULK IN 189
2.18.9 PDMA DESCRIPTOR FORMAT 190
2.18.10 REGISTER DESCRIPTIONS (BASE: 0X1012_0000) 192
2.18.11 USB DEVICE CONTROLLER REGISTERS 192
2.18.12 UDMA REGISTERS 193
2.18.13 PDMA REGISTERS 194
2.19 FRAME ENGINE 202
2.19.1 PSE FEATURES 202
2.19.2 PPE FEATURES 202
2.19.3 PACKET DMA (PDMA) FEATURES 202
2.19.4 BLOCK DIAGRAM 203
2.19.5 PDMA FIFO-LIKE RING CONCEPT 204
2.19.6 PDMA TX DESCRIPTOR FORMAT 205
2.19.7 PDMA RX DESCRIPTOR FORMAT 207
2.19.8 GLOBAL REGISTERS (BASE: 0X1010_0000) 209
2.19.9 CPU PORT REGISTERS (BASE: 0X1010_0400) 216
2.19.10 PDMA REGISTERS (BASE: 0X1010_0800) 223
2.19.11 MIB COUNTER DESCRIPTION (BASE: 0X1010_1000) 235
2.20 ETHERNET SWITCH 237
2.20.1 FEATURES 237
2.20.2 BLOCK DIAGRAM 238
2.20.3 FRAME CLASSFICATION 238
2.20.4 SWITCH L2/L3 ADDRESS TABLE 240
2.20.5 VIRTUAL LAN 244
2.20.6 ACCESS CONTROL LOGIC 247
2.20.7 ARL REGISTERS (BASE: 0X1011_0000) 252
2.20.8 BMU REGISTERS 291
2.20.9 PORT REGISTERS 308
2.20.10 MAC REGISTERS 320
2.20.11 MIB REGISTERS 329
2.20.12 GSW CONFIGURATION REGISTERS 338
2.20.13 MDIO CONTROL 347
2.21 PCI/PCIE CONTROLLER 354
2.21.1 BLOCK DIAGRAM 355
2.21.2 PCIE CONTROLLER ACTING AS A PCIE DEVICE 356
2.21.3 BLOCK DIAGRAM 357
2.21.4 PCI/PCIE MASTER ACCESS IN HOST MODE 358
2.21.5 PCIE CONTROLLER HOST MODE INITIALIZATON EXAMPLE 359
2.21.6 HOST-PCI BRIDGE REGISTERS (BASE: 0X1014_0000) 359
2.21.7 PCIE0 RC CONTROL REGISTERS (BASE: 0X1014_2000) 363